1. Field of the Invention
The present invention generally relates to a MOM capacitor circuit and a semiconductor device thereof, for example a flash memory such as an electrically rewritable non-volatile semiconductor memory device (EEPROM).
2. Description of Related Art
Conventionally, a plurality of memory cell transistors (hereinafter memory cell) are connected in series between the bit line and the source line to constitute a NAND string, so as to achieve a highly integrated NAND-type non-volatile semiconductor memory device known in the art (for example, refer to Patent Document 1).
FIG. 1 is a block diagram showing the overall configuration of a NAND type flash EEPROM according to the conventional art. FIG. 2 is a circuit diagram showing the configuration of a memory cell array 10 of FIG. 1 and its peripheral circuit.
In FIG. 1, the conventional NAND-type flash EEPROM is configured to include a memory cell array 10, a control circuit 11 for operation control, a row decoder 12, a high voltage generating circuit 13, a page buffer circuit 14 that includes data rewriting and reading circuits, a column decoder 15, a command register 17, an address register 18, an operation logic controller 19, a data input/output buffer 50 and a data input/output terminal 51.
As shown in FIG. 2, the memory cell array 10 can for example be composed of NAND cell units NU (NU0, NU1, . . . ) each of which has 16 electrically rewritable non-volatile memory cells MC0˜MC15 with stacked gate structure that are connected in series. In each NAND cell unit NU, the drain side is connected to a bit line BL through a select gate transistor SG1, and the source side is connected to a common source line CELSRC through a select gate transistor SG2. The control gates of the memory cells MC arranged in the row direction are commonly connected to a word line WL, and the gate electrodes of the select gate transistors SG1, SG2 are connected to the select gate lines SGD, SGS that are arranged in parallel with the word line WL. The range of memory cells selected by one word line WL is one page that is the unit for reading and writing. A range of plural NAND cell units NU within one page or its integer multiple range is defined as one block, i.e., the unit for erasing data. The page buffer circuit 14 is used for performing data writing and reading in a page unit, and includes a sense amplifier circuit (SA) and a latch circuit (DL) provided for each bit line.
The memory cell array 10 shown in FIG. 2 has a simplified structure, wherein a plurality of bit lines can shares the page buffer. In this case, the number of bit lines selectively connected to the page buffer during data writing or reading operation will be in a unit of one page. Furthermore, FIG. 2 shows the range of cell array where data input and output is performed with one data input/output terminal 51. In order to perform selection of the word line WL and the bit line BL of the memory cell array 10, the row decoder 12 and the column decoder 15 are provided. The control circuit 11 is used to perform the sequence control for data writing, erasing and reading. The high voltage generating circuit 13, which is controlled by the control circuit 11, will generate a boosted high voltage and intermediate voltage used for data rewriting, erasing and reading.
The data input/output buffer 50 is used to input and output data as well as used to input the address signal. That is, through the data input/output buffer 50 and the data signal line 52, data transfer is performed between the data input/output terminal 51 and the page buffer circuit 14. The address signal that is inputted from the data input/output terminal 51 is maintained in the address register 18, and the signal is sent to the row decoder 12 and the column decoder 15 for decoding. The command for the operation control is also inputted from the data input/output terminal 51. The inputted command is decoded and maintained in the command register 17, and is further used for controlling the control circuit 11. External control signals such as the chip enable signal CEB, the command latch enable CLE, the address latch enable signal ALE, the write enable signal WEB and the read enable signal REB etc. are taken into the operation logic controller 19, wherein the internal control signal is generated according to the operation mode. The internal control signal is used to control the data latch, data transfer in the data input/output buffer 50, and the internal control signal is further sent to the control circuit 11 where the operation control is performed.
The page buffer circuit 14 includes two latch circuits 14a and 14b, and is configured to be capable of switching between the multi-value operation function and the cache function. That is, when one memory cell is used to store a 1 bit binary data, the cache function is provided; when one memory cell is used to store a 2 bit four-value data, either to perform the cache function, or to be limited by address, the cache function can be affected.
FIG. 3A a plan view showing an example configuration of a MOM (Metal-Oxide Metal) capacitor according to the conventional example that is generally formed in a large-scale semiconductor integrated circuit (LSI). FIG. 3B is a vertical cross-sectional view along the line A-A′ shown in FIG. 3A. In FIG. 3A and FIG. 3B, after forming an oxide film 21 such as a silicon oxide film on a semiconductor substrate 20, the metal electrodes 31˜34 of the Nth metal layer MLN are formed on the oxide film 21. Furthermore, after forming an oxide film 22, the metal electrodes 35˜38 of the N+1th metal layer MLN+1 are formed on the oxide film 22. Additionally, after forming an oxide film 23, the metal electrodes 39˜42 of the N+2th metal layer MLN+2 are formed on the oxide film 23. In the manner described above, the capacitor C101 is formed by the pair of metal electrodes 36 and 40 with the oxide film 23 sandwiched therebetween, and the capacitor 102 is formed by the pair of metal electrodes 36 and 37 with the oxide film 23 sandwiched therebetween. In addition a capacitor circuit having such a plurality of MOM capacitors is also formed in a non-volatile memory device such as a NAND type flash memory.